The Chip-Scale Atomic Clock – Low-Power Physics Package - Sponsored Whitepaper

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We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, σy(τ) < 6 x 10-10 τ-1/2, with a total power consumption of less than 30 mW and overall device volume < 1 cm3. In the past year, the development effort has shifted from fundamental research and feasibility investigation to engineering and prototype development. In this paper, we report on the design of a rugged and compact physics package that is expected to exceed the ultimate performance and power requirements of the CSAC.
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